coreboot-3.0.0 Sun Feb 24 10:17:11 EST 2008 starting... Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/initram/segment0 LAR: seen member blob/vsa LAR: seen member zerofill LAR: seen member bootblock LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/initram/segment0 LAR: CHECK normal/initram/segment0 @ 0xfff9ba50 start 0xfff9baa0 len 5372 reallen 5372 compression 0 entry 0x00000f04 loadaddress 0x00000000 Entry point is 0xfff9c9a4 Hi there from stage1 done preinit done gpio init pll_reset: read msr 0x4c000014 _MSR GLCP_SYS_RSTPLL (4c000014) value is: 0000059c:0000182e Configuring PLL Resetting the processor after PLL configuration for the changes to take effect coreboot-3.0.0 Sun Feb 24 10:17:11 EST 2008 starting... Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/initram/segment0 LAR: seen member blob/vsa LAR: seen member zerofill LAR: seen member bootblock LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/initram/segment0 LAR: CHECK normal/initram/segment0 @ 0xfff9ba50 start 0xfff9baa0 len 5372 reallen 5372 compression 0 entry 0x00000f04 loadaddress 0x00000000 Entry point is 0xfff9c9a4 Hi there from stage1 done preinit done gpio init pll_reset: read msr 0x4c000014 _MSR GLCP_SYS_RSTPLL (4c000014) value is: 0000059c:07de002e Done pll_reset done pll reset spd_read_byte dev 00a0 addr 0d returns 08 spd_read_byte dev 00a0 addr 05 returns 01 spd_read_byte dev 00a2 returns 0xff Done cpubug fixes done cpu reg init done sdram set registers spd_read_byte dev 00a0 addr 15 returns ff spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 09 returns 0a spd_read_byte dev 00a2 returns 0xff ========== Check present ======================================================= spd_read_byte dev 00a0 addr 02 returns 07 ========== MODBANKS ============================================================ spd_read_byte dev 00a0 addr 05 returns 01 ========== FIELDBANKS ========================================================== spd_read_byte dev 00a0 addr 11 returns 04 ========== SPDNUMROWS ========================================================== spd_read_byte dev 00a0 addr 03 returns 03 spd_read_byte dev 00a0 addr 04 returns 0a ========== SPDBANKDENSITY ====================================================== spd_read_byte dev 00a0 addr 1f returns 40 ========== BEFORT CTZ ========================================================== ========== TEST DIMM SIZE>8 ==================================================== ========== PAGESIZE ============================================================ spd_read_byte dev 00a0 addr 04 returns 0a ========== MAXCOLADDR ========================================================== ========== RDMSR CF07 ========================================================== ========== WRMSR CF07 ========================================================== ========== ALL DONE ============================================================ ========== Check present ======================================================= spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 12 returns 10 spd_read_byte dev 00a0 addr 17 returns 3c spd_read_byte dev 00a0 addr 19 returns 4b spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 1e returns 28 spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 1b returns 0f spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 1d returns 0f spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 1c returns 0a spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 2a returns 46 spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 16 returns ff spd_read_byte dev 00a2 returns 0xff spd_read_byte dev 00a0 addr 0c returns 3a spd_read_byte dev 00a2 returns 0xff done sdram set spd registers DRAM controller init done. RAM DLL lock done sdram enable stage1 returns run_file returns with 0 Done RAM init code ========== Disable_car: done wbinvd ============================================ Enter northbridge_init_early writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB sysmem_init: enable for 256MBytes Usable RAM: 268304383 bytes sysmem_init: MSR 0x10000028, val 0x2000000f:0xfdf00100 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB SMMGL0Init: 268304384 bytes SMMGL0Init: offset is 0x80400000 SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 sizeram: sizem 0x100MB sysmem_init: enable for 256MBytes Usable RAM: 268304383 bytes sysmem_init: MSR 0x4000002a, val 0x2000000f:0xfdf00100 SMMGL1Init: SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 CPU_RCONF_DEFAULT (1808): 0x04FFFC02:0x10FFDF00 CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 L2 cache enabled GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 Exit northbridge_init_early ========== disable_car: done =================================================== LAR: Attempting to open 'normal/stage2/segment0'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: CHECK normal/stage2/segment0 @ 0xfff91f80 start 0xfff91fd0 len 1 reallen 191788 compression 3 entry 0x00002000 loadaddress 0x0000c9e0 LAR: Compression algorithm #3 (zeroes) used LAR: Attempting to open 'normal/stage2/segment1'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: CHECK normal/stage2/segment1 @ 0xfff91fe0 start 0xfff92030 len 33020 reallen 33020 compression 0 entry 0x00002000 loadaddress 0x00002000 LAR: Compression algorithm #0 (none) used LAR: Attempting to open 'normal/stage2/segment2'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: CHECK normal/stage2/segment2 @ 0xfff9a130 start 0xfff9a180 len 6348 reallen 6348 compression 0 entry 0x00002000 loadaddress 0x0000b100 LAR: Compression algorithm #0 (none) used LAR: Attempting to open 'normal/stage2/segment3'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/initram/segment0 LAR: seen member blob/vsa LAR: seen member zerofill LAR: seen member bootblock LAR: File not found! LAR: load_file: No such file 'normal/stage2/segment3' LAR: load_file_segments: All loaded, entry 0x00002000 Phase 1: Very early setup... Phase 1: done Show all devs... root(Root Device): enabled 1 have_resources 0 initialized 0 cpus: Unknown device path type: 0 cpus(): enabled 1 have_resources 0 initialized 0 apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0 pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0 pci_15_0(PCI: 00:0f.0): enabled 1 have_resources 0 initialized 0 ioport_46(IOPORT: 2e): enabled 1 have_resources 0 initialized 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0 Phase 2: Early setup... dev_phase2: dev root: ops 0x000090c0 ops->phase2_setup_scan_bus 0x00000000 dev_phase2: dev cpus: ops 0x00000000 ops->phase2_setup_scan_bus 0x00000000 dev_phase2: dev apic_0: ops 0x0000c8c0 ops->phase2_setup_scan_bus 0x00000000 dev_phase2: dev pci_1_0: ops 0x0000c920 ops->phase2_setup_scan_bus 0x00000000 dev_phase2: dev pci_15_0: ops 0x0000c980 ops->phase2_setup_scan_bus 0x00000000 dev_phase2: dev ioport_46: ops 0x00000000 ops->phase2_setup_scan_bus 0x00000000 dev_phase2: dev domain_0: ops 0x0000c860 ops->phase2_setup_scan_bus 0x00006d71 Calling phase2 phase2_setup_scan_bus... >> Entering northbridge.c: geodelx_pci_domain_phase2 dev_find_device: find PCI: 1022:2090 dev_id_string: Unknown device ID type: 0 Check Unknown dev_id_string: Unknown device ID type: 0 Check Unknown Check APIC_CLUSTER: 1022:2080 Check PCI: 1022:2080 Check PCI: 1022:2090 found Not Doing chipset_flash_setup() Before VSA: do_vsmbios LAR: Attempting to open 'blob/vsa'. LAR: Start 0xfff80000 len 0x80000 LAR: seen member normal/payload/segment0 LAR: seen member normal/payload/segment1 LAR: seen member normal/payload/segment2 LAR: seen member normal/option_table LAR: seen member normal/stage2/segment0 LAR: seen member normal/stage2/segment1 LAR: seen member normal/stage2/segment2 LAR: seen member normal/initram/segment0 LAR: seen member blob/vsa LAR: CHECK blob/vsa @ 0xfff9cfa0 start 0xfff9cfe0 len 57504 reallen 57504 compression 0 entry 0x00000000 loadaddress 0x00000000 LAR: Compression algorithm #0 (none) used buf ilen 57504 real len 57504ld buf 0x00060000 *buf 186 buf[256k] 0 buf[0x20] signature is b0:10:e6:80 Call real_mode_switch_call_vsm do_vsmbios: VSA2 VR signature verified After VSA: VRC_VG value: 0x0008 Graphics init... VRC_VG value: 0x2808 Finding PCI configuration type. PCI: Using configuration type 1 phase2_setup_scan_bus done Phase 2: Done. Show all devs... root(Root Device): enabled 1 have_resources 0 initialized 0 cpus: Unknown device path type: 0 cpus(): enabled 1 have_resources 0 initialized 0 apic_0(APIC: 00): enabled 1 have_resources 0 initialized 0 pci_1_0(PCI: 00:01.0): enabled 1 have_resources 0 initialized 0 pci_15_0(PCI: 00:0f.0): enabled 1 have_resources 0 initialized 0 ioport_46(IOPORT: 2e): enabled 1 have_resources 0 initialized 0 domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0 initialized 0 Phase 3: Enumerating buses... dev_phase3_scan: scanning root(Root Device) scan_static_bus for root (Root Device) cpus: Unknown device path type: 0 cpus() enabled apic_0(APIC: 00) enabled cs5536: cs5536_pci_dev_enable_resources() pci_dev_enable_resources: pci_15_0 (PCI: 00:0f.0) cmd <- 149 cs5536: cs5536_pci_dev_enable_resources() Exit dev_phase5: ioport_46(IOPORT: 2e) missing ops domain_0(PCI_DOMAIN: 0000) enabled domain_0(PCI_DOMAIN: 0000) scanning... dev_phase3_scan: scanning domain_0(PCI_DOMAIN: 0000) pci_scan_bus start bus 0x0000bdc0, bus->dev 0x0000bb80 PCI: pci_scan_bus for bus 00 pci_scan_bus: old_devices 0x0000be80, dev for this bus 0x0000bb80 (domain_0) PCI: scan devfn 0x0 to 0xff PCI: devfn 0x0 pci_scan_get_dev: list is 0x00087eb8, *list is 0x0000be80 pci_scan_get_dev: check dev pci_1_0 pci_scan_get_dev: check dev pci_1_0 it has devfn 0x08 pci_scan_get_dev: check dev pci_15_0 pci_scan_get_dev: check dev pci_15_0 it has devfn 0x78 pci_scan_get_dev: check dev ioport_46 pci_scan_get_dev: child ioport_46(IOPORT: 2e) not a pci device: it's type 11 PCI: pci_scan_bus pci_scan_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev 0x00000000() PCI: devfn 0x8 pci_scan_get_dev: list is 0x00087eb8, *list is 0x0000be80 pci_scan_get_dev: check dev pci_1_0 pci_scan_get_dev