Output Driver Compensation Control Register
  This register is used to program the drive strength and termination resistance for the DRAM channel.


Processor On-die Termination (ProcOdt) - Bits (29-28)
  This field is used to select the resistance of
      the on-die termination resistors.
      00b = 300 ohms +/- 20%
      01b = 150 ohms +/- 20%.
      10b = 75 ohms +/- 20%.
      11b = Reserved.
                 proprietary-48G-memsettings: 01b (150 ohms +/- 20%.)
             coreboot-48G-667MHz-memsettings: 00b (300 ohms +/- 20%)

Write Data Timing Low Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 3 Timing Control (WrDatTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to byte 3 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 010110b
Write Data Byte 2 Timing Control (WrDatTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to byte 2 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 010111b
Write Data Byte 1 Timing Control (WrDatTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to byte 1 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 010111b
Write Data Byte 0 Timing Control (WrDatTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to byte 0 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 010101b

Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 7 Timing Control (WrDatTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to byte 7 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 010111b
Write Data Byte 6 Timing Control (WrDatTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to byte 6 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 010110b
Write Data Byte 5 Timing Control (WrDatTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to byte 5 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 010011b
Write Data Byte 4 Timing Control (WrDatTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to byte 4 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 011010b

Write Data ECC Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data ECC Timing Control (WrChkTime) - Bits (5-0)
  These bits select how much delay is
      added to the ECC with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 011001b

Address Timing Control Register
  This register controls the time of the address, command, chip select, ODT and clock enable pins with
respect to MEMCLK.


CS/ODT Fine Delay (CsOdtFineDelay) - Bits (12-8)
  These bits control how long the CS and ODT
     pins are delayed from the default setup time.
     00000b = no delay
     00001b = 1/64 MEMCLK delay
     00010b = 2/64 MEMCLK delay
     ...
     11111b = 31/64 MEMCLK delay
                 proprietary-48G-memsettings: 01111b
             coreboot-48G-667MHz-memsettings: 00000b (no delay)
CS/ODT Setup Time (CsOdtSetup) - Bits (13)
  This bit selects the default setup time for the CS and
     ODT pins versus MEMCLK.
     0 = 1/2 MEMCLK
     1 = 1 MEMCLK)
                 proprietary-48G-memsettings: 1b
             coreboot-48G-667MHz-memsettings: 0b

Read DQS Timing Low Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 3 Timing Control (RdDqsTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 3 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 011000b
Read DQS Byte 2 Timing Control (RdDqsTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 2 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 011001b
Read DQS Byte 1 Timing Control (RdDqsTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 1 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 011001b
Read DQS Byte 0 Timing Control (RdDqsTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 0 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 011000b

Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 011001b
Read DQS Byte 4 Timing Control (RdDqsTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 4 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 010111b

Read DQS ECC Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS ECC Byte Timing Control (RdDqsTimeCheck) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with the ECC byte with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 010111b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110100b
             coreboot-48G-667MHz-memsettings: 00000000b

Output Driver Compensation Control Register
  This register is used to program the drive strength and termination resistance for the DRAM channel.


Processor On-die Termination (ProcOdt) - Bits (29-28)
  This field is used to select the resistance of
      the on-die termination resistors.
      00b = 300 ohms +/- 20%
      01b = 150 ohms +/- 20%.
      10b = 75 ohms +/- 20%.
      11b = Reserved.
                 proprietary-48G-memsettings: 01b (150 ohms +/- 20%.)
             coreboot-48G-667MHz-memsettings: 00b (300 ohms +/- 20%)

Write Data Timing Low Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 3 Timing Control (WrDatTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to byte 3 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 2 Timing Control (WrDatTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to byte 2 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 1 Timing Control (WrDatTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to byte 1 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 0 Timing Control (WrDatTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to byte 0 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 7 Timing Control (WrDatTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to byte 7 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 6 Timing Control (WrDatTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to byte 6 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 5 Timing Control (WrDatTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to byte 5 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 4 Timing Control (WrDatTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to byte 4 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010100b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

Write Data ECC Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data ECC Timing Control (WrChkTime) - Bits (5-0)
  These bits select how much delay is
      added to the ECC with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010101b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

Address Timing Control Register
  This register controls the time of the address, command, chip select, ODT and clock enable pins with
respect to MEMCLK.


CS/ODT Fine Delay (CsOdtFineDelay) - Bits (12-8)
  These bits control how long the CS and ODT
     pins are delayed from the default setup time.
     00000b = no delay
     00001b = 1/64 MEMCLK delay
     00010b = 2/64 MEMCLK delay
     ...
     11111b = 31/64 MEMCLK delay
                 proprietary-48G-memsettings: 01111b
             coreboot-48G-667MHz-memsettings: 00000b (no delay)
Address/Command Setup Time (AddrCmdSetup) - Bits (21)
  This bit selects the default setup time
      for the address and command pins versus MEMCLK.
      0 = 1/2 MEMCLK (1 1/2 MEMCLK for 2T timing)
      1 = 1 MEMCLK(2 MEMCLKs for 2T timing)
                 proprietary-48G-memsettings: 1b
             coreboot-48G-667MHz-memsettings: 0b
CS/ODT Setup Time (CsOdtSetup) - Bits (13)
  This bit selects the default setup time for the CS and
     ODT pins versus MEMCLK.
     0 = 1/2 MEMCLK
     1 = 1 MEMCLK)
                 proprietary-48G-memsettings: 1b
             coreboot-48G-667MHz-memsettings: 0b
Address/Command Fine Delay (AddrCmdFineDelay) - Bits (20-16)
  These bits control how long
      the address and command pins are delayed from the default setup time.
      00000b = no delay
      00001b = 1/64 MEMCLK delay
      00010b = 2/64 MEMCLK delay
      ...
      11111b = 31/64 MEMCLK delay
                 proprietary-48G-memsettings: 01111b
             coreboot-48G-667MHz-memsettings: 00000b (no delay)

Read DQS Timing Low Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 3 Timing Control (RdDqsTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 3 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 2 Timing Control (RdDqsTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 2 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 1 Timing Control (RdDqsTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 1 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 0 Timing Control (RdDqsTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 0 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 101111b (47/96 MEMCLK delay)

Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 7 Timing Control (RdDqsTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 7 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011010b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 6 Timing Control (RdDqsTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 6 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 4 Timing Control (RdDqsTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 4 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 101111b (47/96 MEMCLK delay)

Read DQS ECC Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS ECC Byte Timing Control (RdDqsTimeCheck) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with the ECC byte with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110001b
             coreboot-48G-667MHz-memsettings: 00000000b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00111100b
             coreboot-48G-667MHz-memsettings: 01010011b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 01000100b
             coreboot-48G-667MHz-memsettings: 01010011b

Output Driver Compensation Control Register
  This register is used to program the drive strength and termination resistance for the DRAM channel.


Processor On-die Termination (ProcOdt) - Bits (29-28)
  This field is used to select the resistance of
      the on-die termination resistors.
      00b = 300 ohms +/- 20%
      01b = 150 ohms +/- 20%.
      10b = 75 ohms +/- 20%.
      11b = Reserved.
                 proprietary-48G-memsettings: 01b (150 ohms +/- 20%.)
             coreboot-48G-667MHz-memsettings: 00b (300 ohms +/- 20%)

Write Data Timing Low Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 3 Timing Control (WrDatTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to byte 3 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 010101b
Write Data Byte 2 Timing Control (WrDatTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to byte 2 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 010101b
Write Data Byte 1 Timing Control (WrDatTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to byte 1 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 010101b
Write Data Byte 0 Timing Control (WrDatTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to byte 0 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 010101b

Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 7 Timing Control (WrDatTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to byte 7 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 010101b
Write Data Byte 6 Timing Control (WrDatTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to byte 6 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 010101b
Write Data Byte 5 Timing Control (WrDatTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to byte 5 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 010101b
Write Data Byte 4 Timing Control (WrDatTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to byte 4 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 010101b

Write Data ECC Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data ECC Timing Control (WrChkTime) - Bits (5-0)
  These bits select how much delay is
      added to the ECC with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 010101b

Address Timing Control Register
  This register controls the time of the address, command, chip select, ODT and clock enable pins with
respect to MEMCLK.


CS/ODT Fine Delay (CsOdtFineDelay) - Bits (12-8)
  These bits control how long the CS and ODT
     pins are delayed from the default setup time.
     00000b = no delay
     00001b = 1/64 MEMCLK delay
     00010b = 2/64 MEMCLK delay
     ...
     11111b = 31/64 MEMCLK delay
                 proprietary-48G-memsettings: 01111b
             coreboot-48G-667MHz-memsettings: 00000b (no delay)
CS/ODT Setup Time (CsOdtSetup) - Bits (13)
  This bit selects the default setup time for the CS and
     ODT pins versus MEMCLK.
     0 = 1/2 MEMCLK
     1 = 1 MEMCLK)
                 proprietary-48G-memsettings: 1b
             coreboot-48G-667MHz-memsettings: 0b

Read DQS Timing Low Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 3 Timing Control (RdDqsTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 3 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 011001b
Read DQS Byte 2 Timing Control (RdDqsTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 2 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 011000b
Read DQS Byte 1 Timing Control (RdDqsTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 1 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 011001b
Read DQS Byte 0 Timing Control (RdDqsTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 0 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 011000b

Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 7 Timing Control (RdDqsTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 7 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 011001b
Read DQS Byte 6 Timing Control (RdDqsTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 6 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 011010b
Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 010111b
             coreboot-48G-667MHz-memsettings: 011000b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110010b
             coreboot-48G-667MHz-memsettings: 00000000b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00111100b
             coreboot-48G-667MHz-memsettings: 00111011b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 01000110b
             coreboot-48G-667MHz-memsettings: 01000111b

Output Driver Compensation Control Register
  This register is used to program the drive strength and termination resistance for the DRAM channel.


Processor On-die Termination (ProcOdt) - Bits (29-28)
  This field is used to select the resistance of
      the on-die termination resistors.
      00b = 300 ohms +/- 20%
      01b = 150 ohms +/- 20%.
      10b = 75 ohms +/- 20%.
      11b = Reserved.
                 proprietary-48G-memsettings: 01b (150 ohms +/- 20%.)
             coreboot-48G-667MHz-memsettings: 00b (300 ohms +/- 20%)

Write Data Timing Low Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 3 Timing Control (WrDatTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to byte 3 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010101b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 2 Timing Control (WrDatTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to byte 2 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010101b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 1 Timing Control (WrDatTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to byte 1 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010110b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 0 Timing Control (WrDatTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to byte 0 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010101b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 7 Timing Control (WrDatTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to byte 7 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition
                 proprietary-48G-memsettings: 010100b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 6 Timing Control (WrDatTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to byte 6 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010101b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 5 Timing Control (WrDatTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to byte 5 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010101b
             coreboot-48G-667MHz-memsettings: 000000b
Write Data Byte 4 Timing Control (WrDatTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to byte 4 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010100b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

Write Data ECC Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data ECC Timing Control (WrChkTime) - Bits (5-0)
  These bits select how much delay is
      added to the ECC with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010101b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

Address Timing Control Register
  This register controls the time of the address, command, chip select, ODT and clock enable pins with
respect to MEMCLK.


CS/ODT Fine Delay (CsOdtFineDelay) - Bits (12-8)
  These bits control how long the CS and ODT
     pins are delayed from the default setup time.
     00000b = no delay
     00001b = 1/64 MEMCLK delay
     00010b = 2/64 MEMCLK delay
     ...
     11111b = 31/64 MEMCLK delay
                 proprietary-48G-memsettings: 01111b
             coreboot-48G-667MHz-memsettings: 00000b (no delay)
Address/Command Setup Time (AddrCmdSetup) - Bits (21)
  This bit selects the default setup time
      for the address and command pins versus MEMCLK.
      0 = 1/2 MEMCLK (1 1/2 MEMCLK for 2T timing)
      1 = 1 MEMCLK(2 MEMCLKs for 2T timing)
                 proprietary-48G-memsettings: 1b
             coreboot-48G-667MHz-memsettings: 0b
CS/ODT Setup Time (CsOdtSetup) - Bits (13)
  This bit selects the default setup time for the CS and
     ODT pins versus MEMCLK.
     0 = 1/2 MEMCLK
     1 = 1 MEMCLK)
                 proprietary-48G-memsettings: 1b
             coreboot-48G-667MHz-memsettings: 0b
Address/Command Fine Delay (AddrCmdFineDelay) - Bits (20-16)
  These bits control how long
      the address and command pins are delayed from the default setup time.
      00000b = no delay
      00001b = 1/64 MEMCLK delay
      00010b = 2/64 MEMCLK delay
      ...
      11111b = 31/64 MEMCLK delay
                 proprietary-48G-memsettings: 01111b
             coreboot-48G-667MHz-memsettings: 00000b (no delay)

Read DQS Timing Low Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 3 Timing Control (RdDqsTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 3 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 2 Timing Control (RdDqsTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 2 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 1 Timing Control (RdDqsTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 1 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 0 Timing Control (RdDqsTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 0 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 101111b (47/96 MEMCLK delay)

Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 7 Timing Control (RdDqsTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 7 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011011b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 6 Timing Control (RdDqsTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 6 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011011b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 101111b
Read DQS Byte 4 Timing Control (RdDqsTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 4 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011001b
             coreboot-48G-667MHz-memsettings: 101111b (47/96 MEMCLK delay)

Read DQS ECC Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS ECC Byte Timing Control (RdDqsTimeCheck) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with the ECC byte with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
             coreboot-48G-667MHz-memsettings: 000000b (no delay)

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110001b
             coreboot-48G-667MHz-memsettings: 00000000b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00111010b
             coreboot-48G-667MHz-memsettings: 01010011b

DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 01000001b
             coreboot-48G-667MHz-memsettings: 01010011b