0:18.2 01 
Write Data Timing Low Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 3 Timing Control (WrDatTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to byte 3 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Write Data Byte 2 Timing Control (WrDatTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to byte 2 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 011001b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Write Data Byte 1 Timing Control (WrDatTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to byte 1 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 011001b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Write Data Byte 0 Timing Control (WrDatTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to byte 0 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010110b
0:18.2 02 
Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 7 Timing Control (WrDatTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to byte 7 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition
                 proprietary-48G-memsettings: 011001b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Write Data Byte 6 Timing Control (WrDatTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to byte 6 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010110b

Write Data Byte 5 Timing Control (WrDatTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to byte 5 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010110b

Write Data Byte 4 Timing Control (WrDatTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to byte 4 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 011001b
0:18.2 05 
Read DQS Timing Low Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 3 Timing Control (RdDqsTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 3 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 2 Timing Control (RdDqsTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 2 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 1 Timing Control (RdDqsTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 1 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b
0:18.2 06 
Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 6 Timing Control (RdDqsTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 6 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 4 Timing Control (RdDqsTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 4 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b
0:18.2 07 
Read DQS ECC Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS ECC Byte Timing Control (RdDqsTimeCheck) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with the ECC byte with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b
0:18.2 13 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110100b
   coreboot-48G-667MHz-memsettings-20090909h: 00110011b
0:18.2 16 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00111111b
   coreboot-48G-667MHz-memsettings-20090909h: 01100101b
0:18.2 19 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 01000110b
   coreboot-48G-667MHz-memsettings-20090909h: 00100110b
0:18.2 21 
Write Data Timing Low Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 3 Timing Control (WrDatTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to byte 3 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010101b

Write Data Byte 2 Timing Control (WrDatTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to byte 2 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010101b

Write Data Byte 1 Timing Control (WrDatTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to byte 1 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010101b

Write Data Byte 0 Timing Control (WrDatTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to byte 0 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010101b
0:18.2 22 
Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 7 Timing Control (WrDatTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to byte 7 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010100b

Write Data Byte 6 Timing Control (WrDatTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to byte 6 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010110b

Write Data Byte 5 Timing Control (WrDatTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to byte 5 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010101b
0:18.2 23 
Write Data ECC Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data ECC Timing Control (WrChkTime) - Bits (5-0)
  These bits select how much delay is
      added to the ECC with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010101b
   coreboot-48G-667MHz-memsettings-20090909h: 010100b
0:18.2 25 
Read DQS Timing Low Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 3 Timing Control (RdDqsTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 3 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 011000b

Read DQS Byte 2 Timing Control (RdDqsTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 2 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 0 Timing Control (RdDqsTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 0 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011001b
   coreboot-48G-667MHz-memsettings-20090909h: 011010b
0:18.2 26 
Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 4 Timing Control (RdDqsTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 4 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 011001b
0:18.2 33 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110001b
   coreboot-48G-667MHz-memsettings-20090909h: 00110011b
0:18.2 36 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00111100b
   coreboot-48G-667MHz-memsettings-20090909h: 01100101b
0:18.2 39 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 01000100b
   coreboot-48G-667MHz-memsettings-20090909h: 00100100b
0:19.2 02 
Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 4 Timing Control (WrDatTimeByte4) - Bits (5-0)
  These bits select how much
      delay is added to byte 4 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b
0:19.2 03 
Write Data ECC Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data ECC Timing Control (WrChkTime) - Bits (5-0)
  These bits select how much delay is
      added to the ECC with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010110b
0:19.2 06 
Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 6 Timing Control (RdDqsTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 6 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010110b
0:19.2 07 
Read DQS ECC Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS ECC Byte Timing Control (RdDqsTimeCheck) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with the ECC byte with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010111b
   coreboot-48G-667MHz-memsettings-20090909h: 010110b
0:19.2 13 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110010b
   coreboot-48G-667MHz-memsettings-20090909h: 00110001b
0:19.2 16 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00111100b
   coreboot-48G-667MHz-memsettings-20090909h: 00111010b
0:19.2 21 
Write Data Timing Low Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 1 Timing Control (WrDatTimeByte1) - Bits (13-8)
  These bits select how much
      delay is added to byte 1 of the data with respect to DQS. See WrDatTimeByte0 for bit
      definition.
                 proprietary-48G-memsettings: 010110b
   coreboot-48G-667MHz-memsettings-20090909h: 010101b

Write Data Byte 0 Timing Control (WrDatTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to byte 0 of the data with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010101b
   coreboot-48G-667MHz-memsettings-20090909h: 010100b
0:19.2 22 
Write Data Timing High Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data Byte 6 Timing Control (WrDatTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to byte 6 of the data with respect to DQS. See WrDatTimeByte4 for bit
      definition.
                 proprietary-48G-memsettings: 010101b
   coreboot-48G-667MHz-memsettings-20090909h: 010100b
0:19.2 23 
Write Data ECC Timing Control Register
  These registers control the timing of write data with respect to DQS.


Write Data ECC Timing Control (WrChkTime) - Bits (5-0)
  These bits select how much delay is
      added to the ECC with respect to DQS.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 010101b
   coreboot-48G-667MHz-memsettings-20090909h: 010100b
0:19.2 25 
Read DQS Timing Low Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 3 Timing Control (RdDqsTimeByte3) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 3 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 011001b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 2 Timing Control (RdDqsTimeByte2) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 2 with respect to the data. See
      RdDqsTimeByte0 for bit definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 010111b

Read DQS Byte 0 Timing Control (RdDqsTimeByte0) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with byte 0 with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011001b
   coreboot-48G-667MHz-memsettings-20090909h: 011010b
0:19.2 26 
Read DQS Timing High Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS Byte 7 Timing Control (RdDqsTimeByte7) - Bits (29-24)
  These bits select how much
      delay is added to the DQS associated with byte 7 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011011b
   coreboot-48G-667MHz-memsettings-20090909h: 011010b

Read DQS Byte 6 Timing Control (RdDqsTimeByte6) - Bits (21-16)
  These bits select how much
      delay is added to the DQS associated with byte 6 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011011b
   coreboot-48G-667MHz-memsettings-20090909h: 011010b

Read DQS Byte 5 Timing Control (RdDqsTimeByte5) - Bits (13-8)
  These bits select how much
      delay is added to the DQS associated with byte 5 with respect to the data. See
      RdDqsTimeByte4 for bit definition.
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 011001b
0:19.2 27 
Read DQS ECC Timing Control Register
  These registers control how much the read DQS is delayed with respect to the data.


Read DQS ECC Byte Timing Control (RdDqsTimeCheck) - Bits (5-0)
  These bits select how much
      delay is added to the DQS associated with the ECC byte with respect to the data.
      000000b = no delay
      000001b = 1/96 MEMCLK delay
      000010b = 2/96 MEMCLK delay
      ...
      101111b = 47/96 MEMCLK delay
      11xxxxb = reserved
                 proprietary-48G-memsettings: 011000b
   coreboot-48G-667MHz-memsettings-20090909h: 011001b
0:19.2 33 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 00110001b
   coreboot-48G-667MHz-memsettings-20090909h: 00110010b
0:19.2 39 
DQS Receiver Enable Timing Control Register
  These registers specify the delay in picoseconds from the assertion of MEMCLK at the CPU to the
driving of the read preamble by the DIMM as perceived by the CPU. Writing to the DQS receiver
enable timing causes the read and write pointers in the DRAM controller FIFOs to be reset. The DQS
receiver enable delays programmed must meet the following restrictions:
    • The maximum delay between two DIMMs that comprise a logical 128 bit DIMM = 1
        MEMCLK.
    • The delays for unused DIMMs should be programmed to 00h.


DQS Receiver Enable Delay (DqsRcvEnDelay) - Bits (7-0)
  These bits specify the delay in 50
     picosecond increments from the rising edge of MEMCLK at the CPU to the driving of the
     read preamble by the DIMM as perceived at the CPU.
     00h = 0 ps
     01h = 50 ps
     02h = 100 ps
     ...
     AEh = 8.70 ns
     AFh–FFh = Reserved
                 proprietary-48G-memsettings: 01000001b
   coreboot-48G-667MHz-memsettings-20090909h: 01000011b